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Astera LabsSan Jose, California, United States
Technical Lead Design Engineer
On-siteFull Time$133.2k - $185k per yearPosted 20 days ago
About the role
- Astera Labs is hiring a Tech Lead Design Engineer to help architect and deliver the connectivity silicon powering the world’s largest AI clusters
- You’ll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies
- This is a high-impact technical role at a hyper-growth company
- You’ll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap
- If you want to ship silicon that defines AI infrastructure, this is the team
- RTL Design & Implementation
- Own RTL design for assigned blocks from microarchitecture through synthesis sign-off
- Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA
- Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality
- Cross-Functional Execution
- Partner with architecture to translate specifications into implementation-ready microarchitecture
- Collaborate with verification on testplans, coverage closure, and bug triage
- Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure
- Technical Leadership & Quality
- Mentor junior engineers and contribute to design methodology, scripts, and best practices
- Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments
- Drive structured, data-driven design decisions in support of aggressive tapeout schedules Benefits
- Flexible time off in the US
- Parental leave
- 401K
- Retirement and pension plans
- Competitive medical, dental and vision plans
- Hands-on experience with timing closure, CDC, lint, and low-power design techniques
- Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration
- 5+ years of digital design experience, including at least one full chip from spec to tapeout
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
- Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
- MS or PhD in Electrical Engineering or Computer Engineering
- Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs
- Familiarity with formal verification, emulation, or assertion-based methodologies
- Background in advanced process nodes (7nm, 5nm, or below)
- Strong debug skills across pre-silicon and post-silicon environments